The SRAM (static random access memory) is an important semiconductor memory and is widely used in the high-speed data exchange systems such as the computers, communications, multimedia, etc. FIG. 1 illustrates a layout structure of a SRAM cell less than 90 nm. As shown in FIG. 1, the layout structure of a SRAM cell comprises three portions including the active areas, the polysilicon gates and the contact holes. Wherein the numeral 1 represents a Pass Gate, which is an NMOSFET; the numeral 2 represents a Pull Down MOS, which is also an NMOSFET; and the numeral 3 represents a Pull Up MOS, which is a PMOSFET.
The write margin is an important parameter to measure the write performance of the SRAM cells. FIG. 2 is a circuit diagram of a SRAM cell. As illustrated in FIG. 2, the numeral 4 represents a Pass Gate, the numeral 5 represents a Pull Down MOS and the numeral 6 represents a Pull Up MOS. The data stored in the node 7 is assumed to be a low-potential (i.e. the storage data is “0”) and the data stored in the node 8 is assumed to be a high-potential (i.e. the storage data is “1”). An example of writing a high potential to the node 7 and a low potential to the node 8 will be described as follow. Before the write operation, the bit line 9 will be pre-charged to a high potential, and the bit line 10 will be pre-charged to a low potential. At the beginning of the write operation, the word line 11 is turned on. Since the initial data stored in the node 7 is a low potential, the Pull Up MOS 6 is turned on while the Pull Down MOSFET 5 is turned off in the initial state. Therefore, the potential of the node 8 will changes to an intermediate potential instead of “1” as the Pull Up MOS 6 and the Pass Gate 4 are both turned on, wherein the intermediate potential is determined by the equivalent resistances of the Pass Gate 4 and the Pull Up MOS 6. In order to achieve the write operation, the intermediate potential of the node 8 should be less than a certain value, that is, the ratio of the equivalent resistances of the Pass Gate 4 and the Pull Up MOS 6 should be less than a certain value. The lower the intermediate potential is, the greater the write margins of the SRAM cells is. If the equivalent resistance of the Pull Up MOS 6 increases, the intermediate potential of the node 8 will be reduced, thereby increasing the write margins of the SRAM cells.
According to the related advanced process (such as less than 45 nm process), the pre-implantation process for the polysilicon gate will be applied. Before the etching process to the polysilicon layer for forming the polysilicon gate, the fifth-group elements are pre-implanted to the polysilicon layer before forming the NMOSFET gates and the-third group elements are pre-implanted to the polysilicon layer before forming the PMOSFET gate, so as to reduce the gate resistance and the depletion effects of the polysilicon gate, and further to achieve the purpose of adjusting the threshold voltage (Vt) and the open current (Ion) of the CMOS device. In the manufacturing process for the SRAM cells, the process of pre-implanting the fifth-group elements is performed to the two NMOSFETS including the Pass Gate 1 and the Pull Down MOS 2 in FIG. 1; and the process of pre-implanting the third-group elements is performed to the Pull Up MOS (PMOS device) which is the Pull Up MOS 3 in FIG. 1.
However, the write margin of the SRAM cell which is manufactured by the conventional SRAM fabrication method is not satisfying. Thus, it is necessary to provide an effective method to enhance the write margins of the SRAM cells.